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Title:Symbolic techniques for VLSI test and diagnosis
Author(s):Kubiak, Kenneth Edward
Doctoral Committee Chair(s):Fuchs, W. Kent
Department / Program:Electrical and Computer Engineering
Discipline:Electrical and Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Computer Science
Abstract:Many problems in the domain of digital circuit testing and diagnosis demand the processing of a large number of circuit configurations. Recently, due to the development of binary decision diagrams (BDDs), symbolic methods have become a practical means of handling the large sets encountered in these applications. In this thesis, several algorithms are presented which make use of BDDs to address problems in digital circuit testing and diagnosis.
Algorithms are presented for multiple-fault fault simulation, diagnostic fault simulation, test generation, and diagnostic test generation. The algorithms allow the circuit and fault model to be described generally in terms of Boolean functions, and are applicable to hierarchical or partitioned circuits. The procedures necessary to implement deterministic test generation algorithms are specified in terms of the Boolean differential calculus, and this theory provides a basis for test generation at levels of abstraction higher than the gate level. Several operations on BDDs are described which were developed during the course of this work and may be applicable to other domains.
Issue Date:1994
Type:Text
Language:English
URI:http://hdl.handle.net/2142/22776
Rights Information:Copyright 1994 Kubiak, Kenneth Edward
Date Available in IDEALS:2011-05-07
Identifier in Online Catalog:AAI9416388
OCLC Identifier:(UMI)AAI9416388


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