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|Title:||Design and implementation of a multicast, input-buffered ATM switch for theiPOINT testbed|
|Author(s):||Lockwood, John William|
|Doctoral Committee Chair(s):||Kang, Sung Mo|
|Department / Program:||Electrical and Computer Engineering|
|Discipline:||Electrical and Computer Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical
|Abstract:||This thesis presents the design and implementation of the multicast, input-buffered Asynchronous Transfer Mode (ATM) switch for use with the iPOINT testbed. The input-buffered architecture of this switch is optimal in terms of the memory bandwidth required for the implementation of an ATM queue module. The contention resolution algorithm used by the iPOINT switch supports atomic multicast, enabling the simultaneous delivery of ATM cells to multiple output ports without the need for recirculation buffers, duplication of cells in memory, or multiple clock cycles to transfer a cell from an input queue module.
The implementation of the prototype switch is unique in that it was entirely constructed using Field Programmable Gate Array (FPGA) technology. A fully functional, five-port, 800 Mbps ATM switch has been developed and currently serves as the high-speed, optically interconnected, local area network for a cluster of Sun SPARCstations and the gateway to the wide-area Blanca/XUNET gigabit testbed. Through the use of FPGA technology, new hardware-based switching algorithms and functionality can be implemented without the need to modify hard-wired logic. Further, through the use of the remote switch manager, switch controller, and FPGA controller, the management, operation, and even logic functionality of the iPOINT testbed can be dynamically altered, all without the need for physical access to the iPOINT hardware.
Based on the existing prototype switch, the design of the FPGA-based, gigabit-per-second "Any-Queue" module is presented. For this design in its maximum configuration, up to 256 queue modules can be supported, providing an aggregate throughput of 180 Gbps. Further, the design of a 16-port, 11.2 Gbps aggregate throughput, switch fabric is documented that can be entirely implemented using only eight FPGA devices.
In addition to the design of the switch module, this thesis describes the supporting components of the iPOINT testbed, including the network control and application software, the hardware specifications of the switch interface, and the device requirements of the optoelectronic computers used in the testbed
|Rights Information:||Copyright 1996 Lockwood, John William|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9625160|
This item appears in the following Collection(s)
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois