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Title:Diagnosis and correction of logic design errors
Author(s):Chung, Pi-Yu
Doctoral Committee Chair(s):Hajj, Ibrahim N.
Department / Program:Engineering, Electronics and Electrical
Computer Science
Discipline:Engineering, Electronics and Electrical
Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Computer Science
Abstract:A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes corrections automatically.
Our approach is based on the simple design error model proposed by Abadir et al. (1). The model includes eight commonly encountered design errors: simple gate replacement, a missing/extra inverter, a missing/extra gate, a missing/extra gate input and an incorrectly placed gate input. The experiment described in (2) showed that the simple design error model covers 98% of the errors made by designers.
The main contributions of this thesis are (1) developing an efficient and exact search algorithm for single design error; (2) proposing fast gate correction and line correction procedures; and (3) extending the search and correction methods to rectify multiple design errors.
Experimental results on ISCAS and MCNC benchmark circuits show that 100% of single design errors, 68% of two design errors and 54% of three design errors can be corrected by our tool within an hour of CPU time.
Issue Date:1994
Rights Information:Copyright 1994 Chung, Pi-Yu
Date Available in IDEALS:2011-05-07
Identifier in Online Catalog:AAI9416349
OCLC Identifier:(UMI)AAI9416349

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