A design theory for totally self-checking and concurrent error detecting arithmetic circuits

Abstract

This thesis presents the results of an investigation into the applicability of Arithmetic Decomposition Theory (a theory for the design and analysis of arithmetic structures) to the design of concurrent error detecting arithmetic structures. Arithmetic Decomposition Theory shows how large, complex arithmetic circuits can be constructed by interconnecting a number of devices from a small library of elementary modules. The majority of effort in this investigation has gone into extending Arithmetic Decomposition Theory to encompass the design of Totally Self-Checking arithmetic circuits. Totally Self-Checking circuits always either produce a correct output, or give an error indication when a fault in the circuit causes an erroneous output. The extended theory has been demonstrated by its application to the design of a general purpose ALU. A simulator, which is useful in the analysis of Totally Self-Checking arithmetic circuits has been implemented. Finally, an alternative approach to concurrent error detection which involves a generalization of the classic approach of parity prediction to the two dimensional structures of Arithmetic Decomposition Theory has been developed.