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|Title:||Compressed and dynamic fault dictionaries for fault isolation|
|Author(s):||Ryan, Paul George|
|Doctoral Committee Chair(s):||Fuchs, W. Kent|
|Department / Program:||Electrical and Computer Engineering|
|Discipline:||Electrical and Computer Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical|
|Abstract:||This thesis addresses many of the issues that have in the past limited the use of fault dictionaries for VLSI fault isolation. Dictionary formats have been analyzed, and a new, more accurate matching algorithm has been developed. Alternative techniques for compressing fault dictionaries have been investigated to address size and computation cost issues. Two new compression algorithms are presented. List Splitting creates fault dictionaries with a single full fault simulation and provides for rapidly estimating the diagnostic capabilities of a test set. Sequential compression makes no approximations for sequential circuits and thus loses no resolution; however, it costs more than List Splitting, requiring two fault simulations.
Dictionary compression techniques are compared by the size, computation costs and diagnostic resolution of the compressed dictionaries. Results are given for combinational and sequential benchmark circuits, both ISCAS and non-ISCAS. For combinational circuits, List Splitting provides an inexpensive way to produce a small, full resolution fault dictionary. For sequential circuits, List Splitting is effective in compression but does not always provide full resolution. Sequential and Compact provide full resolution, with increased computation costs. When resolution loss is acceptable, Drop on K and a fault grade dictionary have lower simulation costs than a single full simulation.
A new, dynamic two-stage fault isolation process for sequential random logic VLSI circuits is also described in this thesis, along with the two new types of fault dictionaries it uses, Limited and Dynamic dictionaries. The first stage of this process uses a limited fault dictionary to produce a small list of good candidate faults, and the second stage uses dynamic dictionaries to distinguish those faults. This provides adequate resolution for modeled faults, while avoiding a full dictionary's size-related costs.
Two-stage fault isolation has been implemented in simulation for combinational and sequential circuits (both ISCAS and non-ISCAS), and computation time, storage space and resolution have been evaluated. It has also been applied to two industrial circuits, successfully diagnosing both manually injected defects and defects in production chips.
|Rights Information:||Copyright 1994 Ryan, Paul George|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9512534|
This item appears in the following Collection(s)
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois