Browse College of Engineering by Author "Zea, Nicolas"
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Verma, Abhishek; Zea, Nicolas; Cho, Brian; Gupta, Indranil; Campbell, Roy H. (2010-01-19)The MapReduce model uses a barrier between the Map and Reduce stages. This provides simplicity in both programming and implementation. However, in many situations, this barrier hurts performance because it is overly ...
Zea, Nicolas (2010-08-20)Timing speculation has been proposed as a technique for maximizing energy efficiency of processors with minimal loss in performance. A typical implementation of timing speculation involves relaxing the timing constraints ...