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|Title:||Full and approximate modeling of transmission lines for high-speed interconnect simulation|
|Author(s):||Chang, Edward Chongyul|
|Doctoral Committee Chair(s):||Kang, Sung Mo|
|Department / Program:||Engineering, Electronics and Electrical|
|Discipline:||Engineering, Electronics and Electrical|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical|
|Abstract:||This thesis addresses modeling and simulation of high speed interconnects. Both a full transmission line model for accuracy and an approximate model for simulation efficiency are presented. Also techniques to improve simulation efficiency are explained.
The performance of high speed digital integrated circuits with finer feature sizes is limited by the interconnection delay rather than by the device switching time. Transmission line effects such as reflection, dispersion, attenuation and crosstalk can cause false signals, which, in turn, can cause malfunction of the system. Thus accurate modeling and transient simulation of lossy transmission lines have become essential in reliable high speed digital circuit design.
In this thesis, models for both single and coupled transmission lines are developed. Several synthesis techniques to find equivalent circuit models are addressed, including optimization and curve fitting techniques. Since the transient simulation of the lossy transmission lines requires a convolution integral, which becomes quadratically expensive as the simulated time interval increases, techniques to improve its efficiency from quadratic to linear will be presented.
Even though the transmission line model provides the best accuracy, due to its high computational cost, a simpler and faster yet accurate model and a simulation tool are needed to evaluate the timing of high speed digital circuits. Thus, a simplified circuit model based on a combination of Taylor series expansion and Pade synthesis is developed in this thesis. Also iTISET (iLLINOIS Tree Interconnect Structure Evaluation Tool) has been implemented as a stand-alone tool to evaluate an interconnect tree quickly yet accurately.
|Rights Information:||Copyright 1995 Chang, Edward Chongyul|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9624306|
This item appears in the following Collection(s)
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois