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|Title:||A simulation and redesign system for circuit hot-carrier reliability|
|Doctoral Committee Chair(s):||Hajj, Ibrahim N.|
|Department / Program:||Engineering, Electronics and Electrical|
|Discipline:||Engineering, Electronics and Electrical|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical|
|Abstract:||In this thesis a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates circuits to determine the critical transistors that are most susceptible to hot-carrier effect (HCE); it then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE degradation on the performance.
Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-type circuit simulators) for large circuits, and even when fast simulation techniques are used, a user-specified deterministic input waveform is needed. Hence the results can only represent a small sample of operating conditions. In this thesis we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run.
After the simulation phase is completed, the impact of HCE on circuit performance, namely, the increase of delay in digital circuits, is estimated. In this work, we adapt a damaged-transistor model, along with a BDD (Binary Decision Diagram) based critical path identification algorithm, to calculate the delay increase due to HCE. If the performance degradation exceeds a user-specified tolerance limit, several alternative circuit redesign structures can be chosen by the user from a suggested menu. Based on this choice, the system will redesign the critical parts of the circuit to improve circuit performance. Two useful delay optimization methods, transistor reordering and gate sizing, are included in this redesign system.
In this thesis, we present the application of probabilistic simulation to oxide reliability as well. The simulation results demonstrate that our approach can accurately and efficiently predict hot-carrier degradation and oxide stress; the information can be used to improve circuit reliability prior to fabrication.
|Rights Information:||Copyright 1994 Li, Ping-Chung|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9503254|
This item appears in the following Collection(s)
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois