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New strategies for electronic design automation problems

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Title: New strategies for electronic design automation problems
Author(s): Luo, Lijuan
Director of Research: Wong, Martin D. F.
Doctoral Committee Chair(s): Wong, Martin D. F.
Doctoral Committee Member(s): Hwu, Wen-mei W.; Patel, Janak H.; Chen, Deming
Department / Program: Electrical & Computer Eng
Discipline: Electrical & Computer Engr
Degree Granting Institution: University of Illinois at Urbana-Champaign
Degree: Ph.D.
Genre: Dissertation
Subject(s): printed circuit board (PCB) routing escape routing Boolean satisfiability graphics processing unit (GPU) CUDA breadth-first search R-tree
Abstract: As the semiconductor industry marches towards 22 nm technology and beyond, circuit design has become unprecedentedly omplicated. This presents many new challenges for EDA (electronic design automation), such as lack of effective tools for analog circuit or high-volume and high-frequency printed circuit board (PCB) design, the contradiction between complex EDA compute workloads and time-to-market pressure, manufacturing variability and power management, to name but a few. In this dissertation, we will propose several new strategies to handle the challenges in the EDA field. Wire routing is an important step in the design of PCBs. Although there are many industrial tools to handle IC routing problems, very few tools can handle the routing on high-density and high-frequency boards effectively. Nowadays, most of the PCB routing is still done by tedious and time-consuming manual work. We provide new strategies to solve an important problem in PCB routing, the escape routing problem. Our first strategy is to use Boolean satisfiability to optimally solve the escape routing problem on one PCB component. Our second strategy is to use a novel boundary routing methodology to finish escape routing from two connected PCB components simultaneously. This router can achieve much better routability than industrial tools with less CPU time. Another challenge seen in the EDA field is the increasing CPU time to handle larger and larger designs. On the other hand, many fundamental algorithms and data structures used in the EDA tools have shown great parallelism, such as the well-known BFS (breadth-first search) algorithm and the R-tree structure. Therefore, we propose strategies to use the cost-effective GPU platform to parallelize and accelerate BFS and R-tree query. These strategies are potentially applicable to many EDA problems.
Issue Date: 2011-05-25
URI: http://hdl.handle.net/2142/24504
Rights Information: Copyright 2011 Lijuan Luo
Date Available in IDEALS: 2011-05-25
2013-05-26
Date Deposited: 2011-05
 

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