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System-Aware Design of Energy-Efficient High-Speed I/O Links

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Title: System-Aware Design of Energy-Efficient High-Speed I/O Links
Author(s): Lakshmi Narasimha, Rajan
Director of Research: Shanbhag, Naresh
Doctoral Committee Chair(s): Shanbhag, Naresh
Doctoral Committee Member(s): Sarwate, Dilip; Singer, Andrew; Schutt-Aine, Jose
Department / Program: Electrical & Computer Eng
Discipline: Electrical & Computer Engr
Degree Granting Institution: University of Illinois at Urbana-Champaign
Degree: Ph.D.
Genre: Dissertation
Subject(s): energy-efficiency high-speed link forward error correction analog-to-digital converters bit error rate
Abstract: Today's high-speed I/O links operate under stringent specifications: few tens of Gb/s data rates over 20 inches of copper trace, power efficiencies of the order of 10-to-30 mW/Gb/s and a bit error-rate (BER) target of 10^(-12) or lower. State-of-the-art I/O links consist of a transmit driver, PLL, equalizer, clock recovery unit and comparator, primarily implemented with mixed-signal components, to achieve the desired BER without forward error correction (FEC). More recently, analog-to-digital converter (ADC) based receivers have gained acceptance owing to the advantages of digital-intensive designs, viz., their propensity to bene fit from technology scaling and Moore's law. In this thesis, we propose a system-assisted mixed-signal (SAMS) design approach, wherein mixed-signal components of a communication link are designed to meet a system-level performance metric such as BER, in contrast to the component-level design techniques prevalent today. First, we propose FEC-assisted I/O link design, where the FEC coding-gain is leveraged to relax the specifi cations of the mixed-signal components of such links, and achieve improved energy-efficiency. In particular, we demonstrate that FEC coding gain can be leveraged to achieve improvements in transmit driver swing, ADC precision, timing jitter and comparator off set specifi cations necessary to meet the link BER specifi cation. We demonstrate that through a combination of coding and modulation, improvements in link energy-efficiency can be achieved. We propose binary BCH codes, as these codes o ffer sufficient coding gain at moderate to high code-rates, and can be implemented at low power via techniques presented in this thesis. Further, we propose an accurate statistical model to evaluate the impact of FEC on DFE-based links, and employ this model to evaluate random and burst error-correcting binary BCH codes. This is necessary to evaluate FEC performance at the low error rates of interest, where simulations are not feasible. Second, we propose the design of low precision analog-to-digital converters for high-speed I/O links based on the BER metric. In such an ADC, referred to as a BER-optimal ADC, the quantization levels and thresholds are optimized based on BER. We demonstrate the benefi ts of BER-optimal ADCs for typical high-speed I/O links. Further, we propose an adaptation algorithm called AMBER (approximate minimum BER), for quantization levels and thresholds. An architecture to implement this algorithm is proposed and evaluated to prove that this algorithm can be implemented in practice. Finally, we address the issue of creating models for mixed-signal components that would facilitate link optimization based on the SAMS approach. Such a model should capture the system-level behavior of the component when it operates in an unconventional, low-power, error-prone performance envelope. We study the example of a digital latch, which finds widespread application in high-speed ADCs and PLLs. We develop an input-swing dependent fi nite state machine (FSM) model of such a latch in order to capture performance-power trade-o ffs.
Issue Date: 2011-08-25
URI: http://hdl.handle.net/2142/26220
Rights Information: Copyright 2011 Rajan Lakshmi Narasimha
Date Available in IDEALS: 2011-08-25
Date Deposited: 2011-08
 

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