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Title:Input division for binary translation
Author(s):Liu, Geng Daniel
Advisor(s):Hwu, Wen-Mei W.
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Binary translation
Function extraction
Input division
Translation optimization
Abstract:Binary translation is useful in migrating binaries to architectures different from the one they are originally compiled for. The work in this thesis is an optimization of an existing binary translator developed by Chen et al. in 2008. The goal of the binary translator is to allow Android applications with native code compiled for ARM architecture to run on MIPS-based hardware. The ideal time to translate an Android application is when it is being installed. Therefore, the binary translator must execute on a mobile device which has limited compute power. The original binary translator encounters a severe limitation when translating large applications. On those applications, translation takes more than one hour to complete. In the worst case, the translator crashes due to insufficient memory. We present Input Division, an optimization technique that resolves the aforementioned issues. Input Division improved the original implementation with a more advanced input analysis technique that significantly accelerates output binary generation. As a result, we achieved up to 18.9X speedup in translation time and 48X reduction in memory usage.
Issue Date:2012-05-22
Rights Information:Copyright 2012 Geng Daniel Liu
Date Available in IDEALS:2012-05-22
Date Deposited:2012-05

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