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Title:Digital calibration of nonlinear memory errors in sigma-delta ADCs
Author(s):Lee, Seungchul
Director of Research:Chiu, Yun
Doctoral Committee Chair(s):Chiu, Yun
Doctoral Committee Member(s):Feng, Milton; Wong, Martin D.F.; Chen, Deming
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Analog-to-digital converter
ΣΔ modulator
low gain amplifier
nonlinear distortion
memory error
quantization noise leakage
digital calibration
test signal
digital-to-analog converter
capacitor mismatch
piecewise linear model
independent component analysis
multi-stage delta-sigma (MASH) structure
Abstract:Background digital calibration techniques based on an output-referred error model are proposed to linearize sigma-delta (ΣΔ) modulators. A sequential power series (a special form of Volterra series) is found sufficient to model the nonlinear memory errors in a discrete-time integrator (DTI), which entails the application of adaptive polynomial transversal filtering for DTI error correction. For the calibration of feedback digital-to-analog converters, an analog domain pseudorandom noise (PN) removal technique is devised to resolve the input signal dynamic range loss resulting from the PN circulation in modulator loops. Error model identification is accomplished by correlating various moments of the digital output with a one-bit PN by exploiting the independence between the input and injected PN. A 1-0 multi-stage noise shaping SD analog-to-digital converter (ADC) demonstrates the effectiveness/limitation of the proposed digital linearization techniques treating both amplifier distortion and capacitor mismatch in one frame. The design perspectives of low gain two-stage amplifiers are studied with other practical design issues in the implementation. The ADC employing 29 dB gain amplifiers achieves 85 dBc spurious-free dynamic range and 67 dB signal-to-noise ratio for a -1 dBFS (1.1 VPP) 5 MHz sinusoidal input at 240 MS/s and 8 oversampling ratio with the support of digital linearization in which the calibration time is around 7.5 msec. With -6.5 dBFS two-tone signal at 14.9 MHz and 15.1 MHz, the average third order intermodulation after calibration is 87.1 dBc, which is more than 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25 V supply and occupies 0.28 mm2 in a 65 nm CMOS low leakage digital process in which the transistor threshold voltages are around 0.5 V.
Issue Date:2012-09-18
Rights Information:Copyright 2012 Seungchul Lee
Date Available in IDEALS:2012-09-18
Date Deposited:2012-08

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