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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies

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Title: Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
Author(s): Jain, Prabhat
Advisor(s): Torrellas, Josep
Department / Program: Computer Science
Discipline: Computer Science
Degree Granting Institution: University of Illinois at Urbana-Champaign
Degree: M.S.
Genre: Thesis
Subject(s): Static random-access memory (SRAM) Embedded dynamic random-access memory (eDRAM) memory hierarchy computer architecture leakage refresh power
Abstract: As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the opportunity of minimizing on-chip memory power by intelligently refreshing a full-eDRAM cache hierarchy. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and the microarchitecture support. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. Compared to a full-SRAM system, Refrint’s memory hierarchy only consumes 36% of the SRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast, a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’s memory hierarchy energy and induces a slowdown of 18%.
Issue Date: 2012-09-18
URI: http://hdl.handle.net/2142/34585
Rights Information: Copyright 2012 Prabhat Jain
Date Available in IDEALS: 2012-09-18
Date Deposited: 2012-08
 

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