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Title:Automated performance characterization of applications using hardware monitoring events
Author(s):Yoo, Wucherl
Director of Research:Campbell, Roy H.
Doctoral Committee Chair(s):Campbell, Roy H.
Doctoral Committee Member(s):Nahrstedt, Klara; Caesar, Matthew C.; Kuhn, Robert H.
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Performance analysis
resource bottleneck
hardware event
machine learning
Abstract:Applications may have unintended performance problems in spite of compiler optimizations, because of the complexity of the state of the art hardware technologies. Most modern processors incorporate multiple cores that have superscalar, out-of-order, and speculative pipelines. They also have multiple functional units and deeper buffers for sustaining high levels of instruction level parallelism. As the number of cores in modern multiprocessors increase, interactions in, and between, the hardware, operating system, and applications have become increasingly complex. These complexities means that developing applications may include potential performance inefficiencies. Unexpected performance bottlenecks predominantly reside in hardware and suffer from architectural limits. The implemented applications may experience unexpected bottlenecked executions. It is difficult to avoid these performance inefficiencies in applications due to complex interactions in their executions. These complexities make it challenging to identify the performance inefficiencies of applications that suffer from architectural limits. Performance characterization of applications’ hardware behavior is essential for making the best possible use of available hardware resources. Fortunately, modern architectures offer access to many hardware events that are capable of providing information to reveal architectural performance bottlenecks throughout the core and memory hierarchy. These events can provide programmers with unique and powerful insights into the causes of resource bottlenecks in their applications. However, interpreting these events has been a significant challenge. The subject of this thesis is an automated system that uses machine learning to identify an application’s performance problems. Our system provides programmers with insights about the performance of their applications while shielding them from the onerous task of digesting hardware events. It uses a machine learning mechanism, decision tree on our micro-benchmarks in order to fingerprint the performance problems. Decision trees are trained on a sampled set of hardware events to fingerprint the architectural hardware bottlenecks. Our system divides a profiled application into functions using their calling contexts in the hardware event collection. It then automatically classifies each function by dominant hardware resource bottlenecks. Using the classifications from the hotspot functions, we were able to achieve an average speedup of 1.73 from three applications in the PARSEC benchmark suite. Our system provides programmers with a guideline of what, where, and how to fix the detected performance problems in applications, which would have otherwise required considerable architectural knowledge.
Issue Date:2013-02-03
Rights Information:Copyright 2012 Wucherl Yoo
Date Available in IDEALS:2013-02-03
Date Deposited:2012-12

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