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Title:Compilation techniques and language support to facilitate dependence-driven computation
Author(s):Sidelnik, Albert
Director of Research:Padua, David A.; Garzaran, Maria J.
Doctoral Committee Chair(s):Padua, David A.
Doctoral Committee Member(s):Garzaran, Maria J.; Hwu, Wen-Mei W.; Patel, Sanjay J.; Pingali, Keshav; Chamberlain, Bradford L.
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):General-Purpose Computation on Graphics Processing Units (GPGPU)
High Productivity Computing (HPC)
Abstract:As the demand increases for high performance and power efficiency in modern computer runtime systems and architectures, programmers are left with the daunting challenge of fully exploiting these systems for efficiency, high-level expressibility, and portability across different computing architectures. Emerging programming models such as the task-based runtime StarPU and many-core architectures such as GPUs force programmers into choosing either low-level programming languages or putting complete faith in the compiler. As has been previously studied in extensive detail, both development approaches have their own respective trade-offs. The goal of this thesis is to help make parallel programming easier. It addresses these challenges by providing new compilation techniques for high-level programming languages that conform to commonly-accepted paradigms in order to leverage these emerging runtime systems and architectures. In particular, this dissertation makes several contributions to these challenges by leveraging the high-level programming language Chapel in order to efficiently map computation and data onto both the task-based runtime system StarPU and onto GPU-based accelerators. Different loop-based parallel programs and experiments are evaluated in order to measure the effectiveness of the proposed compiler algorithms and their optimizations, while also providing programmability metrics when leveraging high-level languages. In order to exploit additional performance when mapping onto shared memory systems, this thesis proposes a set of compiler and runtime-based heuristics that determine the profitable processor tile shapes and sizes when mapping multiply-nested parallel loops. Finally, a new benchmark-suite named P-Ray is presented. This is used to provide machine characteristics in a portable manner that can be used by either a compiler, an auto-tuning framework, or the programmer when optimizing their applications.
Issue Date:2013-08-22
Rights Information:Copyright 2013 Albert Sidelnik
Date Available in IDEALS:2013-08-22
Date Deposited:2013-08

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