Files in this item



application/pdfCheng-Lin_Tsai.pdf (4MB)
(no description provided)PDF


Title:Carbon nanotube crossbar electrodes for high performance memory devices
Author(s):Tsai, Cheng-Lin
Director of Research:Shim, Moonsub
Doctoral Committee Chair(s):Shim, Moonsub
Doctoral Committee Member(s):Pop, Eric; Rockett, Angus A.; Zuo, Jian-Min
Department / Program:Materials Science & Engineerng
Discipline:Materials Science & Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Carbon nanotube
Raman spectroscopy
Resistive Random Access Memory
Phase Change Memory
Crossbar electrode
Nanoscale heater
Abstract:Two-terminal memories such as Resistive Random Access Memories (RRAMs) and Phase Change Memories (PCMs) are attractive as next generation non-volatile memories due to their low voltage operation and fast switching speed. However, lithographically defined electrodes are difficult to pattern at sub-10 nm dimensions thus limiting the memory density. Carbon nanotubes (CNTs) have been suggested as future materials for nanoscale electrodes and heaters due to their exceptional electrical and thermal properties along with their nanometer dimensions. Integrating CNTs into two-terminal memories are suitable for making smaller, faster, denser, and lower power memories. In addition, vertical cross-point CNT electrodes have the advantages of extremely small bit sizes and precise control of the switching materials thickness, and these elements are important for obtaining high performance memory devices. In Chapter 1, we present Chemical Vapor Deposition (CVD) method to grow CNTs on single crystal quartz substrate, discuss different techniques to transfer CNTs from single crystal quartz substrate to amorphous SiO2 (a-SiO2) substrate, and describe Raman spectroscopy for CNT characterization. In Chapter 2, we develop strategies to achieve a large number of individually electrically addressable CNTs, where majority of these CNTs are semiconducting CNTs. We also demonstrate a new fabrication approach that utilizes Joule heating to create nanotrenches and Cu as an etch mask to improve the yields of individually addressable metallic CNTs, which is more difficult to achieve than semiconducting CNTs using currently available method of electrical breakdown. In Chapter 3, we study heat dissipation in electrically biased individual CNTs on single crystal quartz and a-SiO2 with temperature profiles obtained by spatially resolved Raman spectroscopy. Despite the differences in phonon velocities, thermal conductivity, and van der Waals interactions with CNTs, on average, heat dissipation into single crystal quartz and a-SiO2 is found to be similar. Large temperature gradients and local hot spots often observed underscore the complexity of CNT temperature profiles and may be accountable for the similarities observed. In Chapter 4, we examine AlOx Resistive Random Access Memories (RRAMs) using CNT crossbar electrodes. Both metallic and semiconducting CNTs effectively switch AlOx¬ bits. The low-resistance state scales linearly with CNT series resistance down to ~10 MΩ, at which point the ON-state resistance of the AlOx bit becomes the limiting factor. We demonstrate ON/OFF ratios up to 5×105 and programming currents of 1 to 100 nA with few-Volt set/reset voltages. In Chapter 5, we describe how different oxides affect the doping level in the semiconducting CNTs. With the favorable Fermi level position offset between the CNT and the SnOx, we can achieve more p-doped semiconducting CNTs upon SnOx deposition, leading to a higher electrical conductivity suitable for memory electrodes. In Chapter 6, we measure Ge2Sb2Te5 (GST) Phase Change Memory (PCM) devices using CNT crossbar electrodes. With a possible metallic-metallic junction in the CNT crossbar PCM, remarkably low set/reset currents less than 1 μA and large ON/OFF ratios close to 10000 are demonstrated. However, we can’t obtain reproducible results where PCM devices show multiple switching cycles due to the difficulty of resetting devices. We believe that crystalline halo is created during reset with our device geometry which makes a non-reversible conduction pathway between the top and the bottom CNTs. Forming an extremely thin GST nanowire before making the crossbar may solve this problem. In Chapter 7, we conclude our work with summary and discussion of future directions.
Issue Date:2013-08-22
Rights Information:Copyright 2013 Cheng-Lin Tsai
Date Available in IDEALS:2013-08-22
Date Deposited:2013-08

This item appears in the following Collection(s)

Item Statistics