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Title:Architecture study of a 3D CMOS-NEM FPGA
Author(s):Li, Chong
Advisor(s):Chen, Deming
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Field-Programmable Gate Array (FPGA)
Abstract:In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks (CLBs), NEM-based switch blocks (SBs) and connection blocks (CBs), and face-to-face 3D stacking. This architecture also has a built-in feature named direct link which are dedicated local communication channels using the short vertical wires between the two stacks to further enhance performance. A customized 3D FPGA placement and routing flow and a customized cycle-accurate mixed-level power/thermal simulator have been developed. It is shown that 3D stacking together with NEM devices achieves a 33.11% delay reduction, 29.19% power reduction, and 78.23% footprint reduction over the baseline simultaneously, with negligible temperature penalty.
Issue Date:2013-08-22
Rights Information:Copyright 2013 Chong Li
Date Available in IDEALS:2013-08-22
Date Deposited:2013-08

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