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Title:Optimum gate arrangements for MOS standardized layouts
Author(s):Robbins, David H.
Advisor(s):Mayeda, Watura
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):Field Effect Transistor (FET)
Abstract:Optimization of size is an important topic of research in the engineering of digital circuits. The field effect transistor (FET) is making an important contribution in this area. In this paper, the basic properties of the FET which pertain to digital circuits will be examined. The problems associated with the physical layout of large integrated circuits using FETs will also be discussed and a standardized method of layout will be reviewed. A simple procedure for optimizing chip area when using this standardized layout method will be developed and illustrated.
Issue Date:1975
Type:Text
Language:English
URI:http://hdl.handle.net/2142/45707
Rights Information:Copyright 1975 David H. Robbins
Date Available in IDEALS:2013-09-09


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