Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization

Abstract

Graphene nano-ribbon (GNR) transistors have emerged as a promising candidate to replace traditional silicon transistors in future scaled technologies. Since these devices are very small, the impact of process variation on the circuit’s performance is very large. In this work, we study the impact of process variations on the delay and power of various types of circuits by considering the transistor-level and gate- level impact of the different technology. HSPICE based simulations are per- formed to study smaller circuits and the pros and cons of using GNR transistors. Monte Carlo simulations are performed to analyse the sensitivity of delay and power to the change in transistor parameters and also to analyse the situation when all parameters vary together during fabrication. Standard cell library design and characterisation is also explained, which is essential to perform simulations on large circuits that HSPICE is unable to handle. The standard cell library is also constructed and tested on four circuits to validate the library.