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Title:Noise-Tolerant Circuit Design
Author(s):Ong, Xin Cai
Contributor(s):Shanbhag, Naresh
circuit design
noise-tolerant circuit design
Abstract:Aggressive downscaling of devices into the deep submicron region has inevitably led to smaller supply voltages in devices. As a direct impact of supply voltage scaling, the threshold voltage of devices decreases, magnifying the impact of noise in these circuits. Researchers have hence come up with various noise-tolerant circuit designs in an attempt to increase noise immunity. This however increases power dissipation in circuits, causing it to be a rising concern as devices shrink. In this paper, five noise-tolerant circuit techniques — namely, twin transistor, mirror, noise-tolerant precharge, keeper, and isolated noise-tolerant dynamic circuit — are analyzed using simulation tools such as HSPICE. Implementing each technique for a two-input AND gate, the corresponding noise immunity curve and average noise threshold energy are obtained and compared.
Issue Date:2010-05
Publication Status:unpublished
Peer Reviewed:not peer reviewed
Date Available in IDEALS:2014-01-21

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