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Title:Investigating Charged Device Model Electrostatic Discharge Failures
Author(s):Jaing, Shangliang
Contributor(s):Rosenbaum, Elyse
Subject(s):electrostatic discharge
charge device model
integrated circuit simulation
integrated circuit failure
device failure
Abstract:Metal oxide semiconductor field effect transistor (MOSFET) scaling and more complex design techniques have pushed the capabilities of the microelectronics and the integrated circuit industry. However, these advancements yield an increased likelihood of reliability issues. One such phenomenon is electrostatic discharge (ESD), which is modeled using a Human Body Model (HBM) and a Charged Device Model (CDM). While HBM is well characterized and can be protected against, CDM protection is more challenging. This is due to the higher peak current values and faster rise times. Moreover, CDM is an important issue because the integrated circuit industry is highly automated, making it a more accurate depiction of ESD events. This project seeks to provide better understanding of the effect of CDM ESD on integrated circuits, with a goal being to develop practical design rules in order to prevent circuit failures. To accomplish this we designed a test chip. This circuit was provided with various ESD protection devices, such as GGNMOS, SCRs, and rail clamps, which protect all the I/O pins and interpower domain crossings. After fabrication, a series of CDM tests will be performed and the resulting failures analyzed to discover the protection devices that operate best against CDM. The test chip includes a high speed differential input circuit (receiver) and this circuit uses thin-oxide MOSFET. It is expected that more failures will occur at the thin oxide. This thesis describes the design and layout of the high-speed differential receiver, 50- output driver, saturating amplifier, and pulse shaping circuit.
Issue Date:2008-05
Publication Status:unpublished
Peer Reviewed:not peer reviewed
Date Available in IDEALS:2014-01-27

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