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Title:Design of a phase locked loop based clocking circuit for high speed serial link applications
Author(s):Ratan, Rishi
Advisor(s):Schutt-Ainé, José E.
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Phase locked loops (PLLs)
Serial Links
High Speed
Clocking Circuits
Abstract:Technology scaling and unprecedented growth in demand for ubiquitous, fast, robust computing have been the driving forces leading the innovations in high-speed interfaces. With the rise of heavy duty data centers to handheld mobile devices, the desire for faster, low-power integrated inter-IC communication protocols is at an all-time high and has led the roadmap of the semiconductor industry, making it one of the fastest growing yet fiercely competitive industries. With the growing needs for ultra-low power yet multi-Gbps signaling in both wired as well as wireline applications, integrated systems on chip (SoCs) have become mainstream critical components in modern computing systems. The ability to process and access 'big-data' is the fundamental demand in modern society where every second saved in prompt communication as well as computation of information is critical. In order to meet these needs of fast, robust signaling over the same old ''lossy'' channels, the clock-frequencies need to scale accordingly and clever I/O links need to be developed. The most crucial component of any high-speed I/O link is the clocking circuitry: clock generator at the transmit (TX) end and clock-recovery unit on the receive (RX) end. This thesis provides an in-depth tutorial on circuit design, analysis and simulation of on-chip PLL based clocking generator circuits for high-speed serial link applications. An overview of high-speed links, along with the basic building blocks that make up a serial link, is presented. The fundamentals of PLLs are introduced and a complete guide to analysis and simulation of a charge-pump phase-locked loop based clocking circuit at both behavioral as well as transistor levels is presented for use as a synthesizer in a serial link. Finally, a survey of potential future research areas to explore for both PLLs in high-speed links as well as the complete serial link is provided with an emphasis on signal integrity applications for future students pursuing graduate studies in the fields of Signal Integrity and Mixed-Signal IC Design.
Issue Date:2014-05-30
Rights Information:Copyright 2014 Rishi Ratan
Date Available in IDEALS:2014-05-30
Date Deposited:2014-05

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