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Title:Design of PLL-Based Clock and Data Recovery Circuits for High-Speed SerDes Links
Author(s):Bisht, Ishita
Contributor(s):Schutt-Aine, Jose
Subject(s):high-speed data transmission
SerDes links
phase-locked loop
clock and data recovery circuit
Abstract:Over the years, the thirst for high speeds in data transmission has become unquenchable. Todays demands necessitate operation of transmission links at speeds in the gigahertz range. At such accelerated rates, maintaining signal integrity becomes a challenging task. It is imperative for creditable data links to offer high data accuracy at high speeds. One of the technologies implemented today to achieve high-speed data transmission with signal integrity is the SerDes (Serializer-Deserializer). The SerDes implementation offers the advantage of low manufacturing cost and less crosstalk. In this design the incoming parallel data is mapped onto a single data stream using a serializer before transmission. The serial data is transmitted over the channel along with an embedded clock. The data is received at the other end of the channel and deserialized to generate parallel data output. The data clock is generated by using a phase locked loop (PLL) as a frequency synthesizer. It steps up the clock frequency of a crystal clock to that of the data rate. The data integrity that the SerDes offers is predominantly due to the clock and data recovery circuit (CDR) employed within the design. The CDR takes the incoming data and generates a clock using the data specs which can then be used by the deserializer to sample the data accurately. This thesis looks into the basic principles of operation of phase locked loops, Clock and Data recovery circuits and their building blocks for a 1.6 Gbps SerDes link. It summarizes the challenges in design and also presents a Cadence approach to the circuit design in 180 nm CMOS technology.
Issue Date:2014-05
Genre:Other
Type:Text
Language:English
URI:http://hdl.handle.net/2142/54543
Date Available in IDEALS:2014-09-22


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