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Title:Simple Neuronal Implementation of Self Organizing Maps
Author(s):Findlay, Junia
Contributor(s):Levinson, Stephen
Subject(s):FPGA
ASIC
Self-Organizing Map
Neural Networks
Abstract:The motivation for this research is to be able to replicate a simplified neuronal model onto an FPGA using VHDL logic. Once the artificial neuron is created, self-organizing algorithms (Kohonen Maps) will be implemented. The self-organizing map is a local optimization algorithm. Testing a neuronal model with a self-organizing map on the FPGA will allow us to investigate some of the behavior of these algorithms in a neural basis. How simplified can we make a neuron? Is a self-organizing map a natural topological representation of these artificial neurons? Is utilization of an FPGA more realistic since we would expect noise to contribute to the behavior of our self-organizing map? We first utilized various resources related to self-organizing maps, neural engineering and FPGA design. Create one functioning neuron. We test the neuron to make sure the behavior works as expected and then create our self-organizing map. Testing and implementation will allow us to have beneficial information regarding the benefit or drawback when utilizing that FPGA.
Issue Date:2014-05
Genre:Other
Type:Text
Language:English
URI:http://hdl.handle.net/2142/54550
Date Available in IDEALS:2014-09-22


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