Files in this item
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application/pdf ![]() | Main Tech Report File |
Description
Title: | Response-Time Analysis for Single Core Equivalence Framework |
Author(s): | Mancuso, Renato; Pellizzoni, Rodolfo; Caccamo, Marco; Sha, Lui; Yun, Heechul |
Subject(s): | SCE
multi-core real-time avionics automotive performance isolation inter-core interference hard real-time IMA many-core cache management DRAM management P4080 |
Abstract: | Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. From a real-time perspective, however, the inherent sharing of resources, such as memory subsystem and I/O channels, creates inter-core timing interference among critical tasks and applications deployed on different cores. As a result, modular per-core certification cannot be performed, meaning that: (1) current industrial engineering processes cannot be reused; (2) software developed and certified for single-core chips cannot be deployed on multi-core platforms as is. In this work, we propose the Single Core Equivalence (SCE) technology: a framework of OS-level techniques designed for commercial (COTS) architectures that exports a set of equivalent single-core virtual machines from a multi-core platform. This allows per-core schedulability results to be calculated in isolation and to hold when all the cores of the system are composed together. Thus, SCE allows each core of a multi-core chip to be considered as a conventional single-core chip, ultimately enabling industries to reuse existing software, schedulability analysis methodologies and engineering processes. |
Issue Date: | 2014 |
Genre: | Technical Report |
Type: | Text Dataset / Spreadsheet Image |
Language: | English |
URI: | http://hdl.handle.net/2142/55570 |
Sponsor: | CNS-1302563 CNS-1219064 Lockheed Martin 2009-00524 Rockwell Collins RPS#645038 ONR N00014-12-1-0046 |
Date Available in IDEALS: | 2014-10-28 |