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|Title:||Performance Modeling and Enhancement of the Structured Memory Access Architecture|
|Author(s):||Kahhaleh, Bassam Zuhair|
|Department / Program:||Electrical Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Abstract:||The structured memory access (SMA) architecture solves the traditional von Neumann processor-memory bottleneck by utilizing the structure of a program and the regular ways in which it accesses structured data in memory. The SMA machine consists of two pipelined processors: the computation processor (CP) and the memory access processor (MAP). By storing accessing information in the MAP, the SMA reduces the number of memory references required and utilizes the memory bus more effectively. The von Neumann bottleneck is essentially eliminated by an improved SMA and performance is then limited by process dependencies in the computation processor.
The performance of this architecture is simulated, modeled, and analyzed based on parameters derived from a benchmark program. From the model we define a set of performance degradation factors (PDFs) which degrade the performance of the machine below the maximum performance achievable. Improvements in the machine hardware, based on solving the causes of the major PDFs, are made and shown to reduce the degradation effect of the targeted PDF. Two new functional units in the MAP, an instruction fetching unit (IFU) and a loop control unit (LCU), are used to reduce two major PDFs in the memory and in the MAP, respectively. With the addition of these units, the improved SMA machine tolerates slower memory and utilizes a longer MAP pipeline more effectively. The last major PDF in the system, caused by data dependency in the CP, is significantly reduced by three possible techniques: program restructuring, out-of-order execution, and multistreaming.
From these results, the SMA shows a considerable speedup over a comparable conventional architecture with a serial processor. SMA performance is due to several "architectural features": loop mode, access mechanisms, slip, parallelism, overlap, and pipelining. The individual and combined effects of these features are modeled. A cost-effective design methodology is developed which adds only those features that produce a required performance level at minimum cost. In general, slip and overlap allow the accessing process to run ahead of the computation process and the memory, respectively, thereby permitting effective utilization of high-speed pipelines. The other features enhance performance further.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1984.
|Date Available in IDEALS:||2014-12-15|
This item appears in the following Collection(s)
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois