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Title:Topics in Totally Self-Checking Circuits and Testable Cmos Circuits
Author(s):Jha, Niraj Kumar
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:A Totally Self-Checking (TSC) circuit belongs to a class of circuits used for Concurrent Error Detection (CED) purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives an error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in nMOS, Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are described. Design methods that reduce the transistor count, delay and the number of tests of TSC checkers are also given.
Another problem in the area of TSC circuits concerns embedded checkers whose inputs are not directly controllable. If they do not get all the required codewords to test them, they cannot be guaranteed to be TSC. A new encoding technique and a design procedure to solve this problem are presented.
It has been shown previously that the two-pattern tests used to test CMOS circuits can be invalidated by timing skews. A necessary and sufficient condition is derived to find out whether or not an AND-OR or an OR-AND CMOS realization exists for a given function so that a valid test set can always be found, even in the presence of arbitrary timing skews. A new Hybrid CMOS realization is introduced to take care of the cases in which this is not possible.
Issue Date:1985
Type:Text
Description:108 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.
URI:http://hdl.handle.net/2142/69324
Other Identifier(s):(UMI)AAI8600221
Date Available in IDEALS:2014-12-15
Date Deposited:1985


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