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Title:Use of High-Level Descriptions in Fault Simulation and Test Generation
Author(s):Chang, Hong-Tao Paul
Doctoral Committee Chair(s):Abraham, Jacob A.
Department / Program:Electrical Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Computer Science
Abstract:The goals of this thesis are to study and demonstrate the advantage of using functional descriptions for fault simulation and test generation. By using functional descriptions, high-level functional modules are treated as circuit primitives, as compared with low-level gates and flip-flops which are used in conventional approaches, and the number of primitives elements in a circuit can be significantly reduced. This reduces the computation needed for fault simulation and test generation. In many instances, functional descriptions are also easier to obtain than detailed gate-level implementations. With the functional approach, various fault models can be incorporated as the need arises, which allows more realistic fault models to be used.
The complexity of accurate logic simulation with the existence of unknown values is first studied. It is demonstrated that current gate-level simulators cannot handle unknown propagation properly, and therefore produce pessimistic results. A set of algorithms, based on high-level descriptions of functions, has been developed for accurate logic simulation. Experiments on large benchmark functions show the advantage of using high-level descriptions and provide empirical rules for predicting when approximate simulation would provide satisfactory results.
In Chapter 3, an innovative fault simulation technique is proposed which incorporates high-level circuit descriptions together with high-level fault models to achieve a more efficient, flexible, and accurate fault simulation system. Programmable Logic Arrays (PLAs) and Read Only Memories (ROMs) are chosen as examples for discussion. The proposed technique has been implemented in an existing fault simulation system, CHIEFS. Experiments done on some real PLAs show that, compared with gate-level fault simulation, significant reduction in both time and storage requirements can be achieved using the new technique.
Issue Date:1987
Type:Text
Description:94 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.
URI:http://hdl.handle.net/2142/69367
Other Identifier(s):(UMI)AAI8802994
Date Available in IDEALS:2014-12-15
Date Deposited:1987


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