Files in this item
|(no description provided)|
|Title:||Extraction of MOS VLSI Circuit Models Including Critical Interconnect Parasitics|
|Doctoral Committee Chair(s):||Trick, Timothy N.|
|Department / Program:||Electrical Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical
|Abstract:||As the feature sizes of Very-Large-Scale-Integrated (VLSI) circuits continue to decrease, the timing performance of a design cannot be estimated accurately without introducing the signal delay due to interconnect parasitics. Modeling interconnect parasitics directly from a circuit layout is therefore emphasized.
In this research, two programs, FEMRC and HPEX, have been developed to investigated the following areas: (1) interconnect modeling, (2) hierarchical parasitic circuit extraction, and (3) collapsing technique for interconnects. The FEMRC is a two-dimensional, finite-element program which computes the resistance or the capacitance from the user-specified geometry. Since the equation formulation for FEMRC is based on a finite-element method, there is no shape restrictions on dielectric interfaces or conductor geometries. In resistance calculation, a quasi-three-dimensional effect of contact resistance is also taken into account. The program HPEX is a hierarchical parasitic circuit extractor which takes the CIF layout description as an input and generates a SPICE input with different details of interconnect parasitics. In this extractor, analytical formulas fitted from numerical data are used to model interconnect parasitics of VLSI circuits in order to compromise between the accuracy and the computation time. Simulations show that by carefully fitting data analytical formulas can be very accurate, especially when the interconnect region is fairly regular. Layout partition technique, which facilitates the interconnect modeling, is also studied and implemented in HPEX. Finally, a new node reduction technique which accurately reduces parasitic RC networks is studied. This technique is capable of reducing a large volume of interconnect data into a manageable size, thereby substantially reducing the effort needed in verification.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987.
|Date Available in IDEALS:||2014-12-15|
This item appears in the following Collection(s)
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois