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Title:Minimal Parallel Binary Adders With And/or Gates and a Scheme for a Compact Parallel Multiplier
Author(s):Cheng, Bin
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Computer Science
Abstract:As we enter the era of VLSI, the compactness of logic networks becomes more and more important. A more compact logic network leads to an IC chip of smaller size, lower power consumption, higher speed, and higher yield. We usually design logic networks with a minimum number of gates and a minimum number of connections. This design approach tends to reduce the chip area covered by the network and appears satisfactory if we first use the minimum logic network as a model and then make modifications according to constraints necessary to implement later design stages.
An n-bit parallel binary adder is a logic network which adds two n-bit binary numbers with a carry-in to obtain the n-bit sum with a carry-out. This thesis first presents a way to break the n-bit system to n one-bit adder modules with a well-defined flow of information among them in order to design an n-bit parallel binary adder with a minimum number of gates and a minimum number of connections. The flow of information among one-bit adder modules is not necessarily equivalent to the carry information. The properties of a one-bit adder module are then explored and the one-bit adder modules are subsequently reintegrated into the n-bit parallel binary adder. A minimal n-bit parallel binary adder saves about 2 gates and 1 connection at each stage and is about twice as fast as the convetional carry-ripple adder.
A parallel multiplier is a logic network which multiplies two binary numbers to obtain their product. It carries out the multiplying process in two phases, the generation phase and the summation phase. The generation phase generates partial products using AND gates and the summation phase sums the partial products to obtain the final product using full and half adders. This thesis discusses the interdependency among a certain pattern of partial products and finds don't-cares for these partial products. By making use of these don't-cares, adding modules with fewer gates can be achieved.
Issue Date:1982
Type:Text
Description:182 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1982.
URI:http://hdl.handle.net/2142/69510
Other Identifier(s):(UMI)AAI8302829
Date Available in IDEALS:2014-12-15
Date Deposited:1982


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