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Title:  Minimal Parallel Binary Adders With And/or Gates and a Scheme for a Compact Parallel Multiplier 
Author(s):  Cheng, Bin 
Department / Program:  Computer Science 
Discipline:  Computer Science 
Degree Granting Institution:  University of Illinois at UrbanaChampaign 
Degree:  Ph.D. 
Genre:  Dissertation 
Subject(s):  Computer Science 
Abstract:  As we enter the era of VLSI, the compactness of logic networks becomes more and more important. A more compact logic network leads to an IC chip of smaller size, lower power consumption, higher speed, and higher yield. We usually design logic networks with a minimum number of gates and a minimum number of connections. This design approach tends to reduce the chip area covered by the network and appears satisfactory if we first use the minimum logic network as a model and then make modifications according to constraints necessary to implement later design stages. An nbit parallel binary adder is a logic network which adds two nbit binary numbers with a carryin to obtain the nbit sum with a carryout. This thesis first presents a way to break the nbit system to n onebit adder modules with a welldefined flow of information among them in order to design an nbit parallel binary adder with a minimum number of gates and a minimum number of connections. The flow of information among onebit adder modules is not necessarily equivalent to the carry information. The properties of a onebit adder module are then explored and the onebit adder modules are subsequently reintegrated into the nbit parallel binary adder. A minimal nbit parallel binary adder saves about 2 gates and 1 connection at each stage and is about twice as fast as the convetional carryripple adder. A parallel multiplier is a logic network which multiplies two binary numbers to obtain their product. It carries out the multiplying process in two phases, the generation phase and the summation phase. The generation phase generates partial products using AND gates and the summation phase sums the partial products to obtain the final product using full and half adders. This thesis discusses the interdependency among a certain pattern of partial products and finds don'tcares for these partial products. By making use of these don'tcares, adding modules with fewer gates can be achieved. 
Issue Date:  1982 
Type:  Text 
Description:  182 p. Thesis (Ph.D.)University of Illinois at UrbanaChampaign, 1982. 
URI:  http://hdl.handle.net/2142/69510 
Other Identifier(s):  (UMI)AAI8302829 
Date Available in IDEALS:  20141215 
Date Deposited:  1982 
This item appears in the following Collection(s)

Dissertations and Theses  Computer Science
Dissertations and Theses from the Dept. of Computer Science 
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois