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|Title:||Topological Design of Segmented-Folded Plas|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Abstract:||The Segmented-Folded PLA, a PLA structure featuring array segmentation and folding is introduced. Its features may be exploited at the topological design level to significantly reduce chip area requirements over designs using conventional PLAs. Significant improvement over the original folded PLA concept is obtained through segmentation of the array into multiple blocks.
A practical, automated design system for the topological design of the Segmented-Folded PLA has been designed and implemented. The design system produces an area-efficient PLA implementation from a set of Boolean equations. The key design goals were full automation (if desired), flexibility, support of practical design constraints, and speed to handle real-sized problems in reasonable time. Various simple heuristic algorithms were developed to minimize the PLA area.
Area reduction of over 80% (compared to a conventional PLA design) has been achieved for a typical 100 by 100 PLA. Total execution time for the above case was less than a minute on the VAX 11/780.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1982.
|Date Available in IDEALS:||2014-12-15|