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|Title:||Multicomputer Interconnection Using Word Parallel Shift Register Ring Networks|
|Author(s):||Horton, Kurt Harold|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Abstract:||This thesis surveys existing processor-memory interconnection structures and investigates the word-parallel ring network in detail. It proposes a design for constructing a multimicrocomputer using such a network. The ring network operates as both a memory switch interconnecting processor nodes and shared memory, and as a high speed block transfer medium between nodes. The major limitation of the approach is the loop transit delay, which grows in direct proportion to ring size. Provided the loop time is small enough compared to the memory cycle time the operation will be acceptable. The ring network is attractive when ring clock times are much faster than memory cycle time.
The basic design is studied using both analytic and simulation models. The block transfer operation makes an analytic model intractable, so the simulation model is extended to include the new capability. The models provide three basic performance measures: memory utilization, ring utilization, and shared memory reference delay.
Operating as a memory switch, the request delay is mainly due to transit delay in the ring. Contention for ring entry is minor, while contention for ring exit is more significant because it incurs an additional loop around the ring. A protocol is developed which eliminates indefinite delay in the ring at the expense of slightly increased average delay. In addition, ring exit contention can be reduced by providing sufficient buffering for incoming requests.
The block transfer feature operates independently, and at a lower priority than the memory requests. It can utilize up to 50% of the ring bandwidth subject to availability. The remaining bandwidth is reserved for memory requests to ensure prompt service. Simulation results indicate that active block transfer creates only minimal additional delay for memory requests.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1984.
|Date Available in IDEALS:||2014-12-15|