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|Title:||Translating Data Flow Graphs to Architectures|
|Author(s):||Raj, Vijay Kumar|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Abstract:||Translating a behavioral description of a digital system into an architecture is the initial step in silicon compilation. The behavioral description is in a high level programming language which is converted to a cyclic directed graph, called a data flow graph. Our design system takes this graph as input and translates it to an architecture and a control sequence which together realize the functional definition.
The first step in the translation process is the assignment of priority levels to the nodes of the graph. These nodes represent (amongst other things) operations in the behavioral description. All nodes belonging to the same priority level are executed at the same instant. The second step involves binding nodes of the graph to components of hardware such as operational units, registers and buses through interaction with a hardware data base. In the third step (optimization step), the user discards components from the hardware and the system re-sequences the graph to allow for the discarded hardware.
This approach has enabled us to build a flexible design system which facilitates a thorough search of the design space.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.
|Date Available in IDEALS:||2014-12-15|