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Title:Methods for Cell Compilation With Constraints (Vlsi, Pla, Routing, Silicon)
Author(s):Lursinsap, Chidchanok
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Computer Science
Abstract:One method in solving the VLSI layout problems is a library of standard cells which are used as standard building blocks. Therefore, the design problem is partitioned into two subproblems: (a) decomposition of design into standard cells and (b) placement and routing of standard cells used in the design. The first problem of standard-cell methodology is that library has to be maintained and updated because each cell is usually needed in many different versions. All of them have the same functionality but slightly different in electrical charateristics (time delay, power consumption), geometrical characteristics (height, width) and the position of each input/output. The solution to this problem is a library of parametrized cells.
The second problem with standard cell approach is the extensive area of the chip used by routing. We lay very dense cells and then lose all that gain by extensive routing between the cells. Through-the-cell routing provides the solution.
This dissertation introduces a new direction of layout design based on PLA structure and, also, proposed new and practical solutions to the problems of this new direction. The dissertation discusses the problems of cell compilation with constraints and proposes the practical algorithms for those problems. The main constraints are (1) 4-directional I/O. Any I/O can be specified on the boundary of the cell at any given position in the term of lambda. The compilier is able to handle multi-terminal nets. (2) Through-the-cell Routing. All routes are superimposed on a cell. Routing information is considered to be a part of the functional description. (3) Resizable Device. The entire cell is decomposed symbolically into subcells called parametrized layout macros such as contact, transistor. Each layout macro can be sized according to its delay time and power consumption. (4) No Limitation of Number of Logic Levels. The cell description is able to describe more than two levels (AND-OR) of logic. (5) Pass-transistor term description is included in the language so that precharge, high impedance and dynamic register can be practically implemented in the layout by the designer.
The layout architecture is based on a PLA structure with two layers of metal and one layer of polysilicon and diffusion. The proposed structure of PLA in this dissertation is different from other conventional PLA structures as follows: (1) AND and OR planes are not physically separated but interleaved. (2) Folding is performed by clustering all variables together according to their weights. The weight of any variable depends on the number of terms having that variable. (3) Pull-up transistors are folded by moving them into the unused holes inside a cell. (4) Routing is considered as a part of term layout and is processed simultaneously with the term layout.
Issue Date:1986
Description:141 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.
Other Identifier(s):(UMI)AAI8623360
Date Available in IDEALS:2014-12-15
Date Deposited:1986

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