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Title:Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
Author(s):Shih, Hsi-Ching
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Computer Science
Abstract:Fault collapsing, test generation, and fault simulation were traditionally developed at the gate-level based on the stuck-at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults which need to be considered in the system so that the effort for test generation and fault simulation can be reduced, two fault collapsing techniques (inter-gate fault collapsing and intra-gate fault collapsing) for both nMOS and CMOS circuits including line stuck-at faults, transistor stuck short faults, and transistor stuck open faults are developed in the first part of the research. In the second part of the research, a new methodology is proposed for generating tests at the transistor-level for realistic failures including bridging faults, line open faults, transistor stuck open and stuck short faults, and transistor gate-to-source short and gate-to-drain short faults in CMOS combinational circuits. In the third part of the research, a new MOS fault simulator, called FAUST, is developed to simulate circuits under realistic physical failures; its fault model includes node-short and line-open faults as well as stuck-at faults. This simulator uses a table lookup of the transistor I-V characteristics as well as a newly proposed static concurrent fault simulation technique to simulate both the fault-free circuit and many faulty circuits in one pass. In the fourth part of the research, FAUST is used to identify the problems with tests in some example circuits. It is shown that tests for MOS VLSI circuits will not detect some physical failures, if these tests are derived using only logic-level considerations. A methodology which combines structured design with use of fault simulation tools at the circuit and system levels is proposed as a solution to the testing problem.
Issue Date:1986
Type:Text
Description:109 p.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.
URI:http://hdl.handle.net/2142/69564
Other Identifier(s):(UMI)AAI8701615
Date Available in IDEALS:2014-12-15
Date Deposited:1986


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