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|Title:||Performance Evaluation of Memory Systems for High-Speed Computers|
|Author(s):||Fu, John Wai Cheong|
|Doctoral Committee Chair(s):||Patel, Janak H.|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Abstract:||High speed computer systems pose two significant problems for memory system designers. How to design memory systems to meet the memory access performance required by the processors and how to evaluate proposed memory designs. This thesis addresses these two issues.
Trace driven simulation, in recent years, has become almost the exclusive technique of choice for evaluating memory system designs. This is expected to remain true for the near future. As the processor cycle time decreases memory access performance contributes more to the overall system performance. Memory system designs need to be evaluated in an accurate and time-efficient manner. To obtain typical behavior memory systems should be evaluated using programs that are realistic and representative of typical programs. However, non-trivial programs generate large traces that have a high computation and storage cost in trace driven simulation. This thesis presents a method for accurate and cost effective evaluation of memory systems with trace driven simulation.
Cache memories have proven to be effective in high speed scalar processors but have typically not been used in vector processors because of perceived poor performance with numerically intensive programs. The second part of this thesis describes how cache memories can be effectively used when executing numerical programs on vector and scalar processors, and multiprocessors. The proposed memory systems are evaluated using trace driven simulation and traces from the PERFECT benchmark set.
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1992.
|Date Available in IDEALS:||2014-12-17|