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Title:Hardware acceleration of the SAMtools variant caller
Author(s):Dutro, Brett
Advisor(s):Lumetta, Steven S.
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Computational genomics
Field-Programmable Gate Array (FPGA)
Hardware Acceleration
Variant calling
Abstract:This thesis presents a design for a hardware-accelerated implementation of the SAMtools variant caller on an FPGA. It also includes a performance analysis of the algorithm and a proposed change to its software architecture to improve performance. SAMtools is normally invoked as a two-step command, where the results of samtools mpileup are piped into bcftools call. Profiling their execution revealed that the single most computationally intensive part of the algorithm is the function bcf_call_combine, which is responsible for 23.63% of the execution time of samtools mpileup. In addition, the various functions used for output in samtools mpileup are responsible for a total of 24.58% of its execution time, while functions responsible for handling input in bcftools call accounted for 93.34% of the execution time of that program. Profiling the full command revealed that bcftools call was only responsible for 5.82% of total run time. Both software and hardware approaches were taken to improve the performance of SAMtools. The software approach combined the two parts of the variant calling command into a single executable called mpileup_call. The hardware approach implemented the functions bcf_call_glfgen and bcf_call_combine in a Verilog/SystemVerilog design targeting an Altera Stratix V GX A7 FPGA. Combining the two parts of the command into a single program resulted in a 2.42x speedup. The hardware accelerated version of the combined tool achieved an overall speedup of 2.93x over the base SAMtools workflow.
Issue Date:2015-01-21
Rights Information:Copyright 2014 Brett Dutro
Date Available in IDEALS:2015-01-21
Date Deposited:2014-12

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