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Title:Refresh reduction in dynamic memories
Author(s):Agrawal, Aditya
Director of Research:Torrellas, Josep
Doctoral Committee Chair(s):Torrellas, Josep
Doctoral Committee Member(s):Patel, Sanjay J.; Shanbhag, Naresh; Somasekhar, Dinesh
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):dynamic random-access memory (DRAM)
embedded dynamic random-access memory (eDRAM)
Cache
dynamic memory
refresh
three-dimensional (3D)
stacking
retention time
Through Silicon Vias (TSV)
Thermal Through Silicon Vias (TTSV)
temperature
leakage
variation
spatial
Abstract:An effective approach to reduce the static energy consumption of large on-chip memories is to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic refresh, which ends up consuming substantial energy for large last-level caches. In upcoming architectures that stack a processor die and multiple DRAM dies, DRAM dies experience higher temperatures. Elevated temperatures increase the periodic refresh requirement of DRAM, also a dynamic memory, which increases its energy and hurts processor performance. In this thesis, we propose and evaluate techniques for refresh reduction in dynamic memories. We examine the opportunity of refreshing only the data that will be used in the near future and only if the data has not been recently accessed (and automatically refreshed). We present Refrint, a simple approach to perform fine-grained refresh of on-chip eDRAM multiprocessor cache hierarchies. We show that an eDRAM-based memory hierarchy with Refrint consumes only 30% of the energy of a conventional SRAM-based memory hierarchy, and induces a slowdown of only 6%. In contrast, an eDRAM-based memory hierarchy without Refrint consumes 56% of the energy of the conventional memory hierarchy, inducing a slowdown of 25%. While it is well known that different eDRAM cells exhibit very different charge-retention properties, current systems pessimistically assume worst-case retention times, and refresh all the cells at a conservatively-high rate. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. We show that the retention times of cells in large eDRAM modules exhibit substantial spatial correlation. We propose a mechanism to exploit such correlation to save refresh energy. With simple techniques, we reduce the refresh energy of large eDRAM modules by 20x. The result is that refresh energy is all but eliminated. Finally, we focus on temperature and refresh reduction in 3D processor-memory stacks. We propose the Xylem Thermal Through Silicon Via (TTSV) placement schemes, to reduce the temperature of the DRAM dies and the processor die in the stack. The TTSV placement should respect the DRAM array structure and handle unknown multicore hotspots. The resulting temperature distribution still has a significant spatial variation. Therefore, we propose new DRAM refresh schemes that take advantage of this spatial variation in temperature. Our best Xylem TTSV placement scheme reduces the peak temperature of the DRAM stack by an average of 8.7 C. Combined with the best DRAM refresh scheme we reduce the number of refreshes by an average of 85%.
Issue Date:2015-01-21
URI:http://hdl.handle.net/2142/72970
Rights Information:Copyright 2014 Aditya Agrawal
Date Available in IDEALS:2015-01-21
Date Deposited:2014-12


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