Files in this item

FilesDescriptionFormat

application/pdf

application/pdfB37-1006.pdf (11MB)
(no description provided)PDF

Description

Title:A Minimum Area VLSI Architecture for O(logn) Time Sorting
Author(s):Bilardi, G.; Preparata, F.P.
Subject(s):VLSI complexity
Area-time trade-off
Combination sorting
Bitonic merging
Cube-connected-cycles
Mesh
Orthogonal trees
Optimal algorithms
Parallel computation
Issue Date:1983-11
Publisher:Applied Computation Theory Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG 83-2227, R-1006, ACT-45
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/74207
Sponsor:Joint Services Electronics Program / N00014-79-C-0424
IBM predoctoral Fellowship
Date Available in IDEALS:2015-04-06
2017-07-14


This item appears in the following Collection(s)

Item Statistics