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Title:A Linear-Tune Algorithm for Switch-Level Simulation with Race Detection in a Class of MOS VLSI Circuits
Author(s):Ramachandran, Vijaya
Subject(s):Switch-level simulation
Race detection
Graph algorithms
MOS VLSI
Ternary simulation
Linear-time simulation
NP-completeness
Issue Date:1984-06
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. ACT-48
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/74243
Publication Status:DARPA / ONR N00014-82-K-0549
NSF / ECS-8404866
Date Available in IDEALS:2015-04-06
2017-07-14


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