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Title:An Elementary Theory of Layout Wirability
Author(s):Lipski, Witold, Jr.; Preparata, Franco P.
Subject(s):VLSI
Layout
Conducting layer
Wiring
Two-layer wirability
Knock-knee mode
Layout grid
Tessellations of the plane
Issue Date:1985-03
Publisher:Applied Computation Theory Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. ACT-54
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/74245
Sponsor:Semiconductor Research Corporation / SRC RSCH 84-06-049
Date Available in IDEALS:2015-04-06
2017-07-14


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