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Title:Complexities of Layouts in Three-Dimensional VLSI Circuits
Author(s):Aboelaze, Mokhtar A.; Wah, Benjamin W.
Subject(s):Cost
Graph embedding
One-active-layer layout
Separator
Three-dimensional layout
Undirected graph
Unrestricted layout
VLSI complexity
Volume
Wire length
Issue Date:1987-02
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-87-2212, CSG-63
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/74383
Sponsor:National Science Foundation / DMC 85-19649
Joint Services Electronics Program / N00014-84-C-0149
Egyptian Educational and Cultural Bureau scholarship
Date Available in IDEALS:2015-04-06
2017-07-14


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