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Description
Title: | Timing and Area Optimization for Standard-Cell VLSI Circuit Design |
Author(s): | Chuang, Weitong; Sapatnekar, Sachin S.; Hajj, Ibrahim N. |
Subject(s): | Discrete gate sizing
Clock skew optimization Partitioning MOS VLSI circuits |
Issue Date: | 1993-07 |
Publisher: | Analog and Digital Circuits, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-93-2228, DAC-39 |
Genre: | Report (Grant or Annual) |
Type: | Text |
Language: | English |
Description: | Coordinated Science Laboratory was formerly known as Control Systems Laboratory |
URI: | http://hdl.handle.net/2142/74481 |
Sponsor: | Joint Services Electronics Program / N00014-90-J-1270 |
Date Available in IDEALS: | 2015-04-06 2017-07-14 |