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Title:Evaluating Code Coverage of Assertions by Static Analysis of RTL
Author(s):Athavale, Viraj; Hertz, Samuel; Vasudevan, Shobha
Subject(s):Code coverage
Formal verification
Static analysis
Abstract:Assertions are critical in pre-silicon hardware verification to ensure expected design behavior. While Register Transfer Level (RTL) code coverage can provide a metric for assertion quality, few methods to report it currently exist. We introduce two practical and effective code coverage metrics for assertions - one inspired by test suite code coverage as reported by RTL simulators and the other by assertion correctness in the context of formal verification. We present an algorithm to compute coverage with respect to assertion correctness, by analyzing the Control Flow Graph (CFG) constructed from the RTL source code. Our technique reports coverage in terms of lines of RTL source code which is easier to interpret and can help in efficiently enhancing an assertion suite. We apply our technique to an open source USB 2.0 design and show that our coverage evaluation is efficient and scalable.
Issue Date:2011-10
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-11-2209, CRHC-11-07
Genre:Report (Grant or Annual)
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
Sponsor:Qualcomm Inc. / C5505 Qualcomm 900038673
Date Available in IDEALS:2015-04-06

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