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Title:Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Author(s):Saab, Daniel G.
Subject(s):Logic simulation
Fault simulation
Switch-level logic simulation
VLSI circuits
Symbolic logic expressions
Concurrent fault simulation
Issue Date:1985-09
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-85-2231
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/75217
Sponsor:Semiconductor Research Corporation / SRC-RSCH-84-06-049
Date Available in IDEALS:2015-04-22


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