Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B44-CSG_106.pdf (14MB) |
Description
| Title: | An Accurate Timing Model for Fault Simulation in MOS Circuits |
| Author(s): | Kim, Sungho |
| Subject(s): | Fault simulation
MOS circuits Delay fault testing Timing model SPICE RSIM |
| Issue Date: | 1989-09 |
| Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-89-2229, CSG-106 |
| Genre: | Report (Grant or Annual) |
| Type: | Text |
| Language: | English |
| Description: | Coordinated Science Laboratory was formerly known as Control Systems Laboratory |
| URI: | http://hdl.handle.net/2142/75281 |
| Sponsor: | Semiconductor Research Corporation / 88-DP-109 Joint Services Electronics Program / N00014-84-C-0149 |
| Date Available in IDEALS: | 2015-04-22 2017-07-15 |