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Title:The Design of a VLSI Systolic Array Processor Cell with Concurrent Error Detection
Author(s):Chin, Michael Tsung Sheng
Subject(s):VLSI design
Systolic
Array processor
Concurrent error detection
RESO
Booth's recoding scheme
Prefix carry computation
Issue Date:1982-10
Publisher:Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. CSG-11
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/75283
Sponsor:Naval Electronics Systems Command VHSIC Program / N00039-80-C-0556
Date Available in IDEALS:2015-04-22
2017-07-15


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