Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  83-8534.pdf (48MB) | Full text |
Description
| Title: | A Model for Simulating Physical Failures in MOS VLSI Circuits |
| Author(s): | Banerjee, Prithviraj |
| Subject(s): | Fault models
MOS VLSI circuits Circuit-level simulations Multi-valued algebra Physical failures Functional fault models Logic simulator |
| Issue Date: | 1982-12 |
| Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. CSG-13 |
| Genre: | Report (Grant or Annual) |
| Type: | Text |
| Language: | English |
| Description: | Coordinated Science Laboratory was formerly known as Control Systems Laboratory |
| URI: | http://hdl.handle.net/2142/75291 |
| Sponsor: | Naval Electronics Systems Command VHSIC Program / N00039-80-C-0556 |
| Date Available in IDEALS: | 2015-04-22 2017-07-15 |