Files in this item
| Files | Description | Format |
|---|---|---|
|
application/pdf  B44-CSG_68.pdf (22MB) | (no description provided) |
Description
| Title: | Design and Test of Bit-Serial Multiplier Arrays |
| Author(s): | Scanlon, Joseph Thomas |
| Subject(s): | Bit-serial arrays
Bit-serial multipliers ILAs VLSI Computer architecture |
| Issue Date: | 1987-06 |
| Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
| Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-87-2237, CSG-68 |
| Genre: | Report |
| Type: | Text |
| Language: | English |
| Description: | Coordinated Science Laboratory was formerly known as Control Systems Laboratory |
| URI: | http://hdl.handle.net/2142/75323 |
| Sponsor: | National Science Foundation / NSF CDR 85-22666 Microelectronics and Computer Technology Corporation (MCC) Graduate Research Board, University of Illinois at Urbana-Champaign |
| Date Available in IDEALS: | 2015-04-22 2017-07-15 |