Files in this item

FilesDescriptionFormat

application/pdf

application/pdfB44-CSG_8.pdf (19MB)Restricted to U of Illinois
(no description provided)PDF

Description

Title:A Parallel VLSI Architecture for Sparse Matrix Computation
Author(s):Hsu, Peter Yan-Tek
Subject(s):Physical system simulation
Sparse matrix
VLSI architecture
Parallel processing
Array processor
Resource scheduling
Synchronization
Issue Date:1982-07
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. CSG-8
Genre:Report
Type:Text
Language:English
Description:Coordinated Science Laboratory was formerly known as Control Systems Laboratory
URI:http://hdl.handle.net/2142/75329
Sponsor:Naval Electronics Systems Command VHSIC Program / N00039-80-C-0556
Date Available in IDEALS:2015-04-22
2017-07-15


This item appears in the following Collection(s)

Item Statistics